This invention relates to a memory device, more particularly to a memory device which enables high-speed accessing of a memory system comprising dynamic random access memories (DRAMs).
The conventional system for reducing the access time of the high-capacity memory of a high-speed processor uses a cache memory and a high-speed buffer. The high-speed buffer is positioned between a high-capacity memory system constituted of a DRAM and the processor and serves as an access device for the cache memory. Techniques regarding access of such a cache memory can be found, for example, in Japanese Laid-open No. JP-A-62197842.
The conventional techniques are based fundamentally on the use of a buffer system for speeding up memory access. While they operate with good effect with respect to programs and data which are run or used over long periods of time, they degrade the real-time throughput when used with a system which includes many dynamic implementations in which dynamic factors arise frequently, such as when there are recurrent interruptions accompanied by frequent switching among programs and data. Moreover, the use of a high-speed cache memory increases system cost and requires the use of complex access circuitry, which is also expensive.